Reducing the burden of parallel loop schedulers for many-core processors

Benchmarking Parallel Performance on Many-Core Processors

With the emergence of many-core processor architectures onto the HPC scene, concerns arise regarding the performance and productivity of numerous existing parallel-programming tools, models, and languages. As these devices begin augmenting conventional distributed cluster systems in an evolving age of heterogeneous supercomputing, proper evaluation and profiling of many-core processors must occ...

Parallel Packet Processing on Multi-core and Many- core Processors

The Service-oriented Router (SoR), a highly functional router based on a novel router architecture, enables unprecedented web services traditional routers were unable to provide. The SoR performs Deep Packet Inspection (DPI) to analyze Layer 7 information, which is becoming increasingly difficult due to the substantial increase in Internet traffic. Meanwhile, multi-core processors and general-p...

Parallel space saving on multi- and many-core processors

Given an array A of n elements and a value 2 ≤ k ≤ n, a frequent item or k-majority element is an element occurring in A more than n/k times. The k-majority problem requires finding all of the k-majority elements. In this paper we deal with parallel shared-memory algorithms for frequent items; we present a sharedmemory version of the Space Saving algorithm and we study its behavior with regard ...

Thermal Field Management for Many-core Processors

This paper first presents an analysis of the global thermal field in many core processors in deep nanometer (to 16nm) nodes under power and thermal budget. We show that the thermal field can have significant spatiotemporal non-uniformity along with high maximum temperature. We propose spatiotemporal power multiplexing as a proactive method to reduce spatial and temporal temperature gradients. S...

Defensive Loop Tiling for Multi-core Processors